The following will describe a conventional TFT-LCD module (liquid crystal module) referring to FIG. 18. A TFT-LCD module 501 of FIG. 18 is composed of a group of gate drivers (gate electrode drive circuit) 530, a group of source drivers (source electrode drive circuit) 540, a liquid crystal panel 550, a controller 510, and a liquid crystal power circuit 520.
The group of gate drivers 530 is composed of m gate drivers G1, G2, . . . , and Gm, which are LSI (Large Scale Integrated Circuit) chips of multiple outputs for driving gate bus lines of the liquid crystal panel 550. Each gate driver is mounded on a TCP (Tape Carrier Package) composed of copper foil wiring which is patterned with small intervals on an insulating film called a tape carrier to be described later and a sealing resin provided for the purpose of fixing and guarding the LSI chips.
The group of source drivers 540 is composed of n source drivers S1, S2, . . . , and Sn, which are LSI chips of multiple outputs for driving source bus lines of the liquid crystal panel 550. As with the group of gate drivers G1, G2, . . . , and G3, each source driver is also mounted on the TCP.
The liquid crystal panel 550 can be indicated by an equivalent circuit as shown in FIG. 19. As shown in FIG. 19, the liquid crystal panel 550 is composed of pixels which are disposed in matrix over a liquid crystal layer and TFTs (Thin Film Transistors) for driving the pixels. To the gate electrodes of the TFTs are connected gate bus lines provided in a horizontal direction, and to the source electrodes are connected source bus lines provided in a vertical direction. On the pixel side, electrodes connected to drain electrodes of the TFT constitute display electrodes, and the electrodes which face the display electrodes via the liquid crystal layer constitute common electrodes with respect to all pixels. Between the display electrodes and the gate bus lines is provided an auxiliary capacity.
When a forward voltage is applied to the gate electrodes of the TFTs (usually this is carried out from the group of gate electrodes 530 via gate bus lines), the TFTs are turned ON, and by the voltage applied to the source electrodes (usually this is carried out from the group of source drivers 540 via source bus lines), the liquid crystal load capacity provided between the gate electrodes and common electrodes is charged. When a reverse voltage is applied to the gate electrodes, the TFTs are turned OFF, and the voltage which had been applied to the source bus lines until this point is maintained in the liquid crystal load capacity.
In this manner, by controlling the gate voltage by way of applying a voltage to be written on the source electrodes, the pixels can be maintained at a predetermined voltage. The transmittance of the liquid crystal layer is changed in accordance with this maintained voltage, and as shown in FIG. 20, image display is carried out by projecting light from a backlight on the back side of the liquid crystal layer and by passing the light through a color filter.
The controller 510 carries out a timing control of a scan pulse generated on the group of gate drivers 530 and of a drive control signal on the group of source drivers 540, using as a base an external synchronize signal (from a host system), and supplies timing signals for the group of gate drivers 530, such as a start pulse signal SPG and a clock signal CLG, and timing signals for the group of source drivers 540, such as a start pulse signal SPD and a clock signal CLD. The liquid crystal power circuit 520 is powered by an external power source to supply power or data suitable for the group of gate drivers 530, group of source drivers 540, and the common electrodes of the liquid crystal panel 550, and supplies power source voltages VDD, VCC, and GND, and a video signal VIDEO as an analog video signal.
The following describes the group of gate drivers 530 in more detail referring to FIG. 21 and FIG. 22.
As shown in FIG. 21, the group of gate drivers 530 includes gate drivers G1, G2, . . . , and Gm which are serially connected to each other while being mounted on TCPg1, g2, . . . , and gm, respectively, and makes an electrical connection between the liquid crystal panel 550 and a print substrate. The outer lead terminals of the TCP, which are to be on the input side of the liquid crystal panel 550, are connected to the print substrate, and the outer lead terminals on the output side are connected to the liquid crystal panel 550. Here, FIG. 21 shows the controller 510 as it includes the liquid crystal power circuit 520, and the controller 510 supplies signals to the group of gate drivers 530 generally in a direction from a gate driver at one end of the group of gate drivers 530 to a gate driver at the other end with respect to all signals. Namely, in FIG. 21, the connection mode is such that the input/output terminals SP1, CL1, input terminal RL1, and power terminals VDD1, VCC1, and GND1 of the gate driver G1 of the group of gate drivers 530 are connected to the controller 510, and all signals are first inputted to the gate driver G1, and the output is then inputted to the gate driver G2, and the signals are sequentially supplied to the gate driver Gm one after another, and the signal transfer is carried out using wiring on the print substrate, wiring on the TCP, and internal wiring of each gate driver.
FIG. 22 is a circuit block diagram of one of the gate drivers. Note that, the gate drivers G1, G2, . . . , and Gm all have the same structure and FIG. 22 only shows an arrangement of a single gate driver. The gate driver includes a bidirectional shift register circuit 561, a level shifter circuit 562, an output circuit 563, SP input/output buffers SB1, SB2, CL input/output buffers CB1 and CB2, an inverter 564, input/output terminals SP1, SP2, CL1, CL2, input terminals RL1 and RL2, power terminals VDD1, VDD2, VCC1, VCC2, GND1, GND2, and output terminals Y1, Y2, . . . , and Yi. The following describes the function of each block.
The bidirectional shift register circuit (transfer circuit) 561 includes, for example, a plurality of latch circuits LAT1, LAT2, . . . , and LATi which are serially connected to each other, and carries out a shift operation, by the clock signal CLG to be a horizontal synchronize signal and to be used for the gate drivers, for transferring the start pulse signal SPG which is to be used for the gate drivers and which is generated from a vertical synchronize signal in a direction from a latch circuit LAT1, via a latch circuit LAT2, and onto a latch circuit LATi, or in a direction from the latch circuit LATi, via a latch circuit LAT(i−1), and onto the latch circuit LAT1. Each of the latch circuits LAT1, LAT2, . . . , and LATi serially outputs, at the timing of the shift operation, a selection pulse (source of drive signal) for selecting a pixel on the liquid crystal panel 550 which is driven by a voltage outputted from the group of source drivers 540.
The level shifter circuit 562 is composed of a plurality of level shifter stages (generation stages) LS1, LS2, . . . , and LSi, and receives selection pulses outputted from the corresponding latch circuits LAT1, LAT2, . . . , and LATi, and converts the voltage level to a voltage level required for turning ON or OFF the TFTs to send the output to the output circuit 563. The output circuit 563 is composed of a plurality of output stages (generation stages) OC1, OC2, . . . , and OCi, and takes in signals outputted from the corresponding level shifter stages LS1, LS2, . . . , and LSi for amplification by the internal buffers, and outputs the signals to the gate bus lines from output terminals Y1, Y2, . . . , and Yi. The outputs from the output circuit 563 are pulse signals, and such pulse signals will be called a gate pulse.
As described, the bidirectional shift register circuit 561 is capable of carrying out a switching operation of shift directions, and the switching operation is carried out by the select signal RLG to be supplied to the input terminal RL1 or RL2. The following describes the switching operation of shift directions by the bidirectional shift register 561.
When the start pulse signal SPG is to be shifted in a direction from the latch circuit LAT1, via the latch circuit LAT2, and onto the latch circuit LATi within the bidirectional shift register 561, the input/output terminal SP1 acts as the input terminal, and the start pulse signal SPG inputted is supplied to the bidirectional shift register circuit 561 via the SP input/output buffer SB1. The SP input/output buffer SB1, when the select signal RLG takes one of the logic levels, is activated by a select signal/RLG (RLG bar) which is obtained as the select signal RLG is inverted by the inverter 564, and the SP input/output buffer SB1 comes to have the function of the input buffer. Here, the SP input/output buffer SB2 is activated by the select signal RLG of the above logic level, and comes to have the function of the output buffer.
Further, as with the start pulse signal SPG, the clock signal CLG is also inputted while the input/output terminal CL1 operates as the input terminal, and is supplied to the bidirectional shift register circuit 561 via the CL input/output buffer CB1. The CL input/output buffer CB1, when the select signal RLG takes one of the logic levels, is activated by the select signal/RLG which is obtained as the select signal RLG is inverted by the inverter 564, and the CL input/output buffer CB1 comes to have the function of the input buffer. Here, the CL input/output buffer CB2 is activated by the select signal RLG of the above logic level, and comes to have the function of the output buffer.
When the SP input/output buffers SB1 and SB2 and CL input/output buffers CB1 and CB2 are activated, the bidirectional shift register circuit 561 of multiple stages of for example 40 stages (i=40) conducts the output of the latch circuit of each stage while subsequently shifting the start pulse signal SPG inputted from the input/output terminal SP1 in a direction from the latch circuit LAT1, via the latch circuit LAT2, and onto the latch circuit LAT40 in synchronization with the clock signal CLG inputted from the input/output terminal CL1. The signal outputted from the latch circuit LAT40 on the 40th stage is outputted as a cascade output signal SPGO to be the start pulse signal SPG of the gate driver on the next stage from the input/output terminal SP2 which acts as the output terminal via the SP input/output buffer SB2.
On the other hand, when the select signal RLG takes the other logic level, the shift direction of the bidirectional shift register circuit 561 is switched in a direction from the latch circuit LATi, via the latch circuit LAT(i−1), and onto the latch circuit LAT1, and the start pulse signal SPG is inputted from the input/output terminal SP2 acting as the input terminal, to be supplied to the bidirectional shift register circuit 561 via the SP input/output buffer B2 which acts as the input buffer. Here, the other SP input/output buffer SB1 acts as the output buffer. The clock signal CLG, as with the start pulse signal SPG, is also inputted from the input/output terminal CL2 acting as the input terminal, to be supplied to the bidirectional shift register circuit 561 via the CL input/output buffer CB2 which acts as the input buffer. Here, the CL input/output buffer CB1 acts as the output buffer.
When the signals are inputted from the input/output terminals SP2 and CL1, and the SP input/output buffers SB1 and SB2 and CL input/output buffers CB1 and CB2 activated, the bidirectional shift register circuit 561 of multiple stages of for example 40 stages (i=40) sequentially shifts the stage which conducts the output in a direction from the latch circuit 40, via the latch circuit LAT 39, and onto the latch circuit LAT1, and the signal outputted from the latch circuit LAT1 on the first stage is outputted as the cascade output signal SPGO to be the start pulse signal SPG of the gate driver of the next stage from the input/output terminal SP1 which acts as the output terminal via the SP input/output buffer SB1.
Thus, generally, the start pulse signal SPG is externally inputted only with respect to the gate driver on the first stage of the group of gate drivers 530 installed in the liquid crystal module 501, and to the other gate drivers is inputted the start pulse signal SPG which is generated by the cascade output signal SPGO which was extracted from the last stage of the bidirectional shift register circuit 561 of the gate driver of the preceding stage. The clock signal CLG, as with the start pulse signal SPG, is subsequently transferred to the gate drivers of the following stages one after another in the same direction as that of the start pulse signal SPG.
Note that, in FIG. 22, the power terminals VDD1 and VDD2 are terminals, one of which is a terminal which receives an output voltage and the other is a terminal for supplying an output voltage to the gate driver of the next stage, and the power terminals VCC1 and VCC2 are terminals, one of which is a terminal which receives a drive voltage for the gate driver and the other is a terminal for supplying the drive voltage to the gate driver of the next stage, and power terminals GND1 and GND2 are terminals, one of which is a terminal which receives a GND potential and the other is a terminal for supplying the GND potential to the gate driver of the next stage.
The above described the gate drivers.
The following describes the source drivers constituting the group of source drivers 540. FIG. 23 is a circuit block diagram of one of the source drivers. Note that, the source drivers S1, S2, . . . , and Sm all have the same structure and FIG. 23 only shows an arrangement of a single source driver. The source driver includes a bidirectional shift register circuit 571, an output circuit 572, SP input/output buffers SB1′, SB2′, CL input/output buffers CB1′ and CB2′, an inverter 573, input/output terminals SP1′, SP2′, CL1′, CL2′, input terminals RL1′ and RL2′, video input terminal Video, power terminals VCC1′, VCC2′, GND1′, GND2′, and output terminals Y1′, Y2′, . . . , and Yi′. The following describes the function of each block.
The bidirectional shift register circuit 571 includes a plurality of latch circuits LAT1′, LAT2′, . . . , and LATi′ which are serially connected to each other as with the gate drivers, and carries out a shift operation by the clock signal CLD for transferring the start pulse signal SPD which is to be used for the source drivers in a direction from a latch circuit LAT1′, via a latch circuit LAT2′, and onto a latch circuit LATi′, or in a direction from the latch circuit LATi′, via a latch circuit LAT(i−1)′, and onto the latch circuit LAT1′. Each of the latch circuits LAT1′, LAT2′, . . . , and LATi′ serially outputs a sampling pulse (source of drive signal) for sampling an analog video signal to the output circuit 572.
The output circuit 572 is composed of a plurality of output stages (generation stages) OC1′, OC2′, . . . , and OCi′, and samples the analog video signal inputted from the video input terminal Video based on sampling pulses outputted from the latch circuits LAT1′, LAT2′, . . . , and LATi′. The sampled signal is amplified by an amplifier circuit provided in the output circuit and is outputted from output terminals Y1′, Y2′, . . . , and Yi′.
As described, the bidirectional shift register circuit 571 is capable of carrying out a switching operation of shift directions as with the gate drivers, and the switching operation is carried out by the select signal RLD to be supplied to the input terminal RL1′ or RL2′. The following describes the switching operation of shift directions by the bidirectional shift register 571.
When the start pulse signal SPD is to be shifted in a direction from the latch circuit LAT1′, via the latch circuit LAT2′, and onto latch circuit LATi′ within the bidirectional shift register 571, the input/output terminal SP1′ acts as the input terminal, and the start pulse signal SPD inputted is supplied to the bidirectional shift register circuit 571 via the SP input/output buffer SB1′. The SP input/output buffer SB1′, when the select signal RLD takes one of the logic levels, is activated by a select signal/RLD (RLD bar) which is obtained as the select signal RLD is inverted by the inverter 573, and the SP input/output buffer SB1′ comes to have the function of the input buffer. Here, the SP input/output buffer SB2′ is activated by the select signal RLD of the above logic level, and comes to have the function of the output buffer.
Further, as with the start pulse signal SPD, the clock signal CLD is also inputted from the input/output terminal CL1′ which functions as the input terminal, and is supplied to the bidirectional shift register circuit 571 via the CL input/output buffer CB1′. The CL input/output buffer CB1′, when the select signal RLD takes one of the logic levels, is activated by the select signal/RLD which is obtained as the select signal RLD is inverted by the inverter 573, and the CL input/output buffer CB1′ comes to have the function of the input buffer. Here, the CL input/output buffer CB2′ is activated by the select signal RLD of the above logic level, and comes to have the function of the output buffer.
When the SP input/output buffers SB1′ and SB2′ and CL input/output buffers CB1′ and CB2′ are activated, the bidirectional shift register circuit 571 of multiple stages of for example 40 stages (i=40) conducts the output of the latch circuit of each stage while subsequently shifting the start pulse signal SPD inputted from the input/output terminal SP1′ in a direction from the latch circuit LAT1′, latch circuit LAT2′, to the latch circuit LAT40′ in synchronization with the clock signal CLD inputted from the input/output terminal CL1′. The signal outputted from the latch circuit LAT40′ on the 40th stage is outputted as a cascade output signal SPGO to be the start pulse signal SPD of the source driver on the next stage from the input/output terminal SP2′ which acts as the output terminal via the SP input/output buffer SB2′.
On the other hand, when the select signal RLD takes the other logic level, the shift direction of the bidirectional shift register circuit 571 is switched in a direction from the latch circuit LATi′, via the latch circuit LAT(i−1)′, and onto the latch circuit LAT1′, and the start pulse signal SPD is inputted from the input/output terminal SP2′ acting as the input terminal to be supplied to the bidirectional shift register circuit 571 via the SP input/output buffer SB2′ which acts as the input buffer. Here, the other SP input/output buffer SB1′ acts as the output buffer. The clock signal CLD, as with the start pulse signal SPD, is also inputted from the input/output terminal CL2′ acting as the input terminal, to be supplied to the bidirectional shift register circuit 571 via the CL input/output buffer CB2′ which acts as the input buffer. Here, the CL input/output buffer CB1′ acts as the output buffer.
When the signals are inputted from the input/output terminals SP2′ and CL1′, and the SP input/output buffers SB1′ and SB2′ and CL input/output buffers CB1′ and CB2′ activated, the bidirectional shift register circuit 571 of multiple stages of for example 40 stages (i=40) sequentially shifts the stage which conducts the output in a direction from the latch circuit LAT40′, via the latch circuit LAT39′, and onto the latch circuit LAT1′, and the signal outputted from the latch circuit LAT1′ on the first stage is outputted as the cascade output signal SPGO to be the start pulse signal SPD of the source driver of the next stage from the input/output terminal SP1′ which acts as the output terminal via the SP input/output buffer SB1′.
Thus, generally, the start pulse signal SPD is externally inputted only with respect to the source driver on the first stage of the group of source drivers 540 installed in the liquid crystal module 501, and to the other source drivers is inputted the start pulse signal SPD which is generated by the cascade output signal SPGO which was extracted from the last stage of the bidirectional shift register circuit 571 of the source driver of the preceding stage. The clock signal CLD, as with the start pulse signal SPD, is subsequently transferred to the source drivers of the following stages one after another in the same direction as that of the start pulse signal SPD.
Note that, in FIG. 23, the power terminals VCC1′ and VCC2′ are terminals, one of which is a terminal which receives a drive voltage for the source driver and the other is a terminal for supplying the drive voltage to the source driver of the next stage, and the power terminals GND1′ and GND2′ are terminals, one of which is a terminal which receives a GND potential and the other is a terminal for supplying the GND potential to the source driver of the next stage.
The above described the source drivers.
In the described prior art, the driver LSIs such as gate drivers and source drivers are serially connected to each other, and this causes malfunction of the liquid crystal driving to occur by the clock skew of the clock signals CLG and CLD, which is generated before and after the input/output buffers CB1, CB2, CB1′, and CB2′. The following describes this problem referring to FIG. 24 and FIG. 25.
FIG. 24 is a circuit block diagram showing a state in which the driver LSIs are serially connected to each other. The circuit block as shown in FIG. 24 may be applied to both the gate drivers and source drivers, and the structure may be regarded as the same for both types of drivers. As such, the driver LSIs are assumed to be the gate drivers and the connection shown here is of a gate driver Gk (k=1, 2, . . . , and m−1) and a gate driver G(k+1).
The bidirectional shift register circuit 561 of the gate driver Gk and gate driver G(k+1) is structured to have a state in which flip-flops of multiple stages from flip-flop F/F1 to flip-flop F/Fi are connected to each other as a latch circuit. In the bidirectional shift register 561 of the gate driver Gk, D terminal and Q terminal of adjacent flip-flops are connected to each other, and the Q terminal of the flip-flop F/Fi on the last stage extends outside via the SP input/output buffer SB1, and is connected to the D terminal of the flip-flop F/F1 on the first stage of the gate driver G(k+1) via the SP input/output buffer SB1.
The clock signal line CL in the gate driver Gk extends outside via the CL input/output buffer CB2, and is connected to the clock signal line in the gate driver G(k+1). The clock signal CLG is supplied to the CK terminals of the gate drivers Gk and G(k+1) and to the internal logic circuit from the clock signal lines.
The input/output mode of the SP input/output buffers SB1 and SB2 and CL input/output buffers CB1 and CB2 of the gate drivers Gk and G(k+1) is controlled by the select signal RLG so that the start pulse signal SPG and clock signal CLG are transferred from the gate driver Gk to gate driver G(k+1). FIG. 24 shows a state of buffer circuits under this control. Thus, the start pulse signal SPG is sequentially transferred from the flip-flop on the left side of the paper to the flip-flop on the right side in synchronization with the rise of the clock signal CLG supplied. Further, in this case, Q output of each flip-flop is also outputted to the level shifter circuit 562, and in the case where the driver LSIs are source drivers, the Q output is also outputted to the output circuit 572.
Here, it is assumed that the clock signal CLG in the gate driver Gk is signal CK1, the start pulse signal SPG inputted to D terminal of the flip-flop F/F(i−1) is signal D1, the start pulse signal SPG outputted from Q terminal of the flip-flop F/F(i−1) and inputted to D terminal of the flip-flop F/Fi is signal D2, the start pulse signal SPG outputted from Q terminal of the flip-flop F/Fi is signal D3, the clock signal CLG in the driver G(k+1) is signal CK2, the start pulse signal SPG inputted to D terminal of the flip-flop F/F1 is signal D4, and the start pulse signal SPG outputted from Q terminal of the flip-flop F/F1 and inputted to D terminal of the flip-flop F/F2 is signal D5.
Then, the timing chart of these signals can be represented as shown in FIG. 25. As shown in FIG. 25, the signal CK1 becomes the signal CK2 via the CL input/output buffers CB1 and CB2, and as a result the signal CK2 is delayed with respect to the signal CK1, and the signal D3 becomes the signal D4 via the SP input/output buffers SB2 and SB1, and as a result the signal D4 is delayed with respect to the signal D3.
Here, the delay time of the clock signal CLG becomes greater than the delay time of the start pulse signal SPG due to waveform rounding as induced by a large negative capacity of the clock signal line and due to the delay time of the buffer circuit with an enhanced driving ability. Thus, when the start pulse signal SPG transferred in synchronization with the rise of signal CK1 through the gate driver Gk is transferred at the rise of signal CK2 in the flip-flop F/F1 on the first stage, there occurs a timing shift of a latch by the delay time, and as shown in FIG. 25, the signal D5 is outputted at a timing with substantially one clock cycle earlier than the timing at which the signal D5 should be outputted. As a result, in the subsequent operation, the start pulse signal SPG is transferred while maintaining this incorrectness and there occurs malfunction of the liquid crystal module 501. This phenomenon also occurs in the source drivers having the same structure.
In general, a demand for increasing the number of pixels is strong to improve the display quality of the liquid crystal module, and in order to meet this demand, the number of stages of the bidirectional shift register of the driver LSI of a single chip is inevitably increased. As a result, increase in load capacity of the clock signal line further aggravates the waveform rounding and delay of the clock signal. Further, because the data signal and clock signal need to be made faster to keep up with the increased number of pixels, the timing control of these signals are becoming harder than ever. Further, to meet the demand of lower power consumption, it is essential that the drive voltage be reduced.
For these reasons, in timing control, there is a limit in conventional techniques in which the load capacity is reduced by micro technique, and in which the driving capacity of the input/output buffer circuit of the clock signal is enhanced to meet the demand of various conditions such as above required for the liquid crystal module, and such conventional techniques involve difficulty in design of mounting as a liquid crystal module.